Chip bug is a potential threat

Increasing sophistication of computer chip design raises the risk that undetected bugs could be used to crack public key encryption systems. With the increasing word size and sophisticated optimizations of multiplication units in modern microprocessors, it becomes alarming that they contain some undetected bugs.

System simulation is used to comprehensively verify that the chip operates correctly in its targeted system configurations under all stress conditions. This method of verification complements unit-level simulation in that it covers the interaction of the unit with its neighbors, as unit-level simulation alone does not. There are two main disadvantages of system simulation: First, it is often difficult to create specific events from outside the chip at the interface of a unit that is deep inside the chip; second, simulations run slowly because of the large compiled simulation image.

Coverage metrics can be used to help quantify which design functions have been reached by simulation. Code-coverage metrics that determine whether each line of Very high-speed integrated circuit Hardware Description Language (VHDL) code has been exercised provide some value, but they provide no means of determining the context in which the line of VHDL was exercised.

There are many other methods to reduce the chances of any unattended bug but still any method does not guarantee 100% free of bugs chip.

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